Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:13.2 (ISE) - O.61xd Target Family: Spartan6
OS Platform: NT64 Target Device: xc6slx9
Project ID (random number) f588f00868f0480eb8e4b89866a19951.b7fb42fb333943d8b7ec8227f0f39cb2.1 Target Package: tqg144
Registration ID 135256_15690819_173552794_661 Target Speed: -2
Date Generated 2012-05-06T20:15:04 Tool Flow CommandLine
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release major release (build 7600)
CPU Name Intel(R) Core(TM) i3-2310M CPU @ 2.10GHz CPU Speed 2095 MHz
OS Name Microsoft Windows 7 , 64-bit OS Release major release (build 7600)
CPU Name Intel(R) Core(TM) i3-2310M CPU @ 2.10GHz CPU Speed 2095 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Registers=1
  • Flip-Flops=1
 		MiscellaneousStatistics
  • AGG_BONDED_IO=13
  • AGG_IO=13
  • AGG_LOCED_IO=1
  • AGG_SLICE=125
  • NUM_BONDED_IOB=13
  • NUM_BSCAN=1
  • NUM_BSFULL=180
  • NUM_BSLUTONLY=72
  • NUM_BSREGONLY=77
  • NUM_BSUSED=329
  • NUM_BUFG=2
  • NUM_LOCED_IOB=1
  • NUM_LOGIC_O5ANDO6=24
  • NUM_LOGIC_O5ONLY=47
  • NUM_LOGIC_O6ONLY=86
  • NUM_LUT_RT_DRIVES_CARRY4=21
  • NUM_LUT_RT_DRIVES_FLOP=28
  • NUM_LUT_RT_EXO5=26
  • NUM_LUT_RT_EXO6=21
  • NUM_LUT_RT_O5=12
  • NUM_LUT_RT_O5ANDO6=2
  • NUM_LUT_RT_O6=47
  • NUM_RAMB16BWER=2
  • NUM_RAMB8BWER=1
  • NUM_SLICEL=30
  • NUM_SLICEM=15
  • NUM_SLICEX=80
  • NUM_SLICE_CARRY4=33
  • NUM_SLICE_CONTROLSET=50
  • NUM_SLICE_CYINIT=354
  • NUM_SLICE_F7MUX=9
  • NUM_SLICE_F8MUX=2
  • NUM_SLICE_FF=305
  • NUM_SLICE_LATCH=1
  • NUM_SLICE_UNUSEDCTRL=7
  • NUM_SRL_O5ANDO6=5
  • NUM_SRL_O6ONLY=41
  • NUM_UNUSABLE_FF_BELS=275
  • Xilinx Core chipscope_icon_v1_05_a, Xilinx CORE Generator 13.2=1
  • Xilinx Core chipscope_ila_v1_04_a, Xilinx CORE Generator 13.2=1
  • Xilinx Core dds_compiler_v4_0, Xilinx CORE Generator 13.2=1
 		NetStatistics
  • NumNets_Active=462
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=15
  • NumNodesOfType_Active_BOUNCEIN=82
  • NumNodesOfType_Active_BUFGOUT=2
  • NumNodesOfType_Active_BUFHINP2OUT=8
  • NumNodesOfType_Active_CLKPIN=118
  • NumNodesOfType_Active_CLKPINFEED=12
  • NumNodesOfType_Active_CNTRLPIN=111
  • NumNodesOfType_Active_DOUBLE=437
  • NumNodesOfType_Active_GENERIC=13
  • NumNodesOfType_Active_GLOBAL=57
  • NumNodesOfType_Active_INPUT=122
  • NumNodesOfType_Active_IOBIN2OUT=12
  • NumNodesOfType_Active_IOBOUTPUT=12
  • NumNodesOfType_Active_LUTINPUT=616
  • NumNodesOfType_Active_OUTBOUND=458
  • NumNodesOfType_Active_OUTPUT=461
  • NumNodesOfType_Active_PADINPUT=12
  • NumNodesOfType_Active_PADOUTPUT=1
  • NumNodesOfType_Active_PINBOUNCE=346
  • NumNodesOfType_Active_PINFEED=894
  • NumNodesOfType_Active_QUAD=241
  • NumNodesOfType_Active_REGINPUT=166
  • NumNodesOfType_Active_SINGLE=721
  • NumNodesOfType_Gnd_BOUNCEIN=29
  • NumNodesOfType_Gnd_HGNDOUT=16
  • NumNodesOfType_Gnd_INPUT=48
  • NumNodesOfType_Gnd_LUTINPUT=12
  • NumNodesOfType_Gnd_OUTBOUND=2
  • NumNodesOfType_Gnd_OUTPUT=2
  • NumNodesOfType_Gnd_PINBOUNCE=39
  • NumNodesOfType_Gnd_PINFEED=55
  • NumNodesOfType_Gnd_REGINPUT=17
  • NumNodesOfType_Gnd_SINGLE=2
  • NumNodesOfType_Vcc_CNTRLPIN=3
  • NumNodesOfType_Vcc_HVCCOUT=50
  • NumNodesOfType_Vcc_INPUT=115
  • NumNodesOfType_Vcc_KVCCOUT=27
  • NumNodesOfType_Vcc_LUTINPUT=210
  • NumNodesOfType_Vcc_PINBOUNCE=19
  • NumNodesOfType_Vcc_PINFEED=313
  • NumNodesOfType_Vcc_REGINPUT=4
 SiteStatistics
  • BUFG-BUFGMUX=2
  • IOB-IOBM=5
  • IOB-IOBS=8
  • SLICEL-SLICEM=12
  • SLICEX-SLICEL=15
  • SLICEX-SLICEM=15
 		SiteSummary
  • BSCAN=1
  • BSCAN_BSCAN=1
  • BUFG=2
  • BUFG_BUFG=2
  • CARRY4=33
  • FF_SR=51
  • HARD0=2
  • HARD1=10
  • IOB=13
  • IOB_IMUX=1
  • IOB_INBUF=1
  • IOB_OUTBUF=12
  • LUT5=110
  • LUT6=179
  • LUT_OR_MEM5=6
  • LUT_OR_MEM6=47
  • PAD=13
  • RAMB16BWER=2
  • RAMB16BWER_RAMB16BWER=2
  • RAMB8BWER=1
  • RAMB8BWER_RAMB8BWER=1
  • REG_SR=255
  • SELMUX2_1=11
  • SLICEL=30
  • SLICEM=15
  • SLICEX=80
 
Configuration Data
BSCAN_BSCAN
  • JTAG_CHAIN=[1:1]
  • JTAG_TEST=[0:1]
 FF_SR
  • CK=[CK:51] [CK_INV:0]
  • SRINIT=[SRINIT0:47] [SRINIT1:4]
  • SYNC_ATTR=[ASYNC:32] [SYNC:19]
 IOB_OUTBUF
  • DRIVEATTRBOX=[12:12]
  • SLEW=[SLOW:12]
  • SUSPEND=[3STATE:12]
 LUT_OR_MEM5
  • CLK=[CLK:5] [CLK_INV:0]
  • LUT_OR_MEM=[LUT:1] [RAM:5]
  • RAMMODE=[SRL16:5]
 LUT_OR_MEM6
  • CLK=[CLK:46] [CLK_INV:0]
  • LUT_OR_MEM=[LUT:1] [RAM:46]
  • RAMMODE=[SRL16:17] [SRL32:29]
 RAMB16BWER
  • CLKA=[CLKA_INV:0] [CLKA:2]
  • CLKB=[CLKB_INV:0] [CLKB:2]
  • ENA=[ENA_INV:0] [ENA:2]
  • ENB=[ENB_INV:0] [ENB:2]
  • REGCEA=[REGCEA_INV:0] [REGCEA:2]
  • REGCEB=[REGCEB_INV:0] [REGCEB:2]
  • RSTA=[RSTA:2] [RSTA_INV:0]
  • RSTB=[RSTB:2] [RSTB_INV:0]
  • WEA0=[WEA0:2] [WEA0_INV:0]
  • WEA1=[WEA1:2] [WEA1_INV:0]
  • WEA2=[WEA2:2] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:2]
  • WEB0=[WEB0:2] [WEB0_INV:0]
  • WEB1=[WEB1:2] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:2]
  • WEB3=[WEB3:2] [WEB3_INV:0]
 RAMB16BWER_RAMB16BWER
  • CLKA=[CLKA_INV:0] [CLKA:2]
  • CLKB=[CLKB_INV:0] [CLKB:2]
  • DATA_WIDTH_A=[9:1] [18:1]
  • DATA_WIDTH_B=[9:1] [18:1]
  • DOA_REG=[0:1] [1:1]
  • DOB_REG=[0:1] [1:1]
  • ENA=[ENA_INV:0] [ENA:2]
  • ENB=[ENB_INV:0] [ENB:2]
  • EN_RSTRAM_A=[FALSE:1] [TRUE:1]
  • EN_RSTRAM_B=[FALSE:1] [TRUE:1]
  • RAM_MODE=[TDP:2]
  • REGCEA=[REGCEA_INV:0] [REGCEA:2]
  • REGCEB=[REGCEB_INV:0] [REGCEB:2]
  • RSTA=[RSTA:2] [RSTA_INV:0]
  • RSTB=[RSTB:2] [RSTB_INV:0]
  • RSTTYPE=[SYNC:2]
  • RST_PRIORITY_A=[CE:2]
  • RST_PRIORITY_B=[CE:2]
  • WEA0=[WEA0:2] [WEA0_INV:0]
  • WEA1=[WEA1:2] [WEA1_INV:0]
  • WEA2=[WEA2:2] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:2]
  • WEB0=[WEB0:2] [WEB0_INV:0]
  • WEB1=[WEB1:2] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:2]
  • WEB3=[WEB3:2] [WEB3_INV:0]
  • WRITE_MODE_A=[WRITE_FIRST:2]
  • WRITE_MODE_B=[WRITE_FIRST:2]
 RAMB8BWER
  • CLKAWRCLK=[CLKAWRCLK:1] [CLKAWRCLK_INV:0]
  • CLKBRDCLK=[CLKBRDCLK_INV:0] [CLKBRDCLK:1]
  • ENAWREN=[ENAWREN:1] [ENAWREN_INV:0]
  • ENBRDEN=[ENBRDEN_INV:0] [ENBRDEN:1]
  • REGCEA=[REGCEA_INV:0] [REGCEA:1]
  • REGCEBREGCE=[REGCEBREGCE_INV:0] [REGCEBREGCE:1]
  • RSTA=[RSTA:1] [RSTA_INV:0]
  • RSTBRST=[RSTBRST:1] [RSTBRST_INV:0]
  • WEAWEL0=[WEAWEL0:1] [WEAWEL0_INV:0]
  • WEAWEL1=[WEAWEL1_INV:0] [WEAWEL1:1]
  • WEBWEU0=[WEBWEU0:1] [WEBWEU0_INV:0]
  • WEBWEU1=[WEBWEU1:1] [WEBWEU1_INV:0]
 RAMB8BWER_RAMB8BWER
  • CLKAWRCLK=[CLKAWRCLK:1] [CLKAWRCLK_INV:0]
  • CLKBRDCLK=[CLKBRDCLK_INV:0] [CLKBRDCLK:1]
  • DATA_WIDTH_A=[4:1]
  • DATA_WIDTH_B=[4:1]
  • DOA_REG=[0:1]
  • DOB_REG=[0:1]
  • ENAWREN=[ENAWREN:1] [ENAWREN_INV:0]
  • ENBRDEN=[ENBRDEN_INV:0] [ENBRDEN:1]
  • EN_RSTRAM_A=[FALSE:1]
  • EN_RSTRAM_B=[FALSE:1]
  • RAM_MODE=[TDP:1]
  • REGCEA=[REGCEA_INV:0] [REGCEA:1]
  • REGCEBREGCE=[REGCEBREGCE_INV:0] [REGCEBREGCE:1]
  • RSTA=[RSTA:1] [RSTA_INV:0]
  • RSTBRST=[RSTBRST:1] [RSTBRST_INV:0]
  • RSTTYPE=[SYNC:1]
  • RST_PRIORITY_A=[CE:1]
  • RST_PRIORITY_B=[CE:1]
  • WEAWEL0=[WEAWEL0:1] [WEAWEL0_INV:0]
  • WEAWEL1=[WEAWEL1_INV:0] [WEAWEL1:1]
  • WEBWEU0=[WEBWEU0:1] [WEBWEU0_INV:0]
  • WEBWEU1=[WEBWEU1:1] [WEBWEU1_INV:0]
  • WRITE_MODE_A=[WRITE_FIRST:1]
  • WRITE_MODE_B=[WRITE_FIRST:1]
 REG_SR
  • CK=[CK:254] [CK_INV:1]
  • LATCH_OR_FF=[FF:254] [LATCH:1]
  • SRINIT=[SRINIT0:222] [SRINIT1:33]
  • SYNC_ATTR=[ASYNC:140] [SYNC:115]
 SLICEL
  • CLK=[CLK:30] [CLK_INV:0]
 SLICEM
  • CLK=[CLK:15] [CLK_INV:0]
 SLICEX
  • CLK=[CLK:72] [CLK_INV:1]
 
Pin Data
BSCAN
  • DRCK=1
  • SEL=1
  • SHIFT=1
  • TDI=1
  • TDO=1
  • UPDATE=1
 BSCAN_BSCAN
  • DRCK=1
  • SEL=1
  • SHIFT=1
  • TDI=1
  • TDO=1
  • UPDATE=1
 BUFG
  • I0=2
  • O=2
 BUFG_BUFG
  • I0=2
  • O=2
 CARRY4
  • CIN=21
  • CO0=4
  • CO3=21
  • CYINIT=12
  • DI0=29
  • DI1=26
  • DI2=23
  • DI3=21
  • O0=25
  • O1=25
  • O2=22
  • O3=19
  • S0=33
  • S1=29
  • S2=26
  • S3=23
 FF_SR
  • CE=8
  • CK=51
  • D=51
  • Q=51
  • SR=23
 HARD0
  • 0=2
 HARD1
  • 1=10
 IOB
  • I=1
  • O=12
  • PAD=13
 IOB_IMUX
  • I=1
  • OUT=1
 IOB_INBUF
  • OUT=1
  • PAD=1
 IOB_OUTBUF
  • IN=12
  • OUT=12
 LUT5
  • A1=2
  • A2=7
  • A3=11
  • A4=17
  • A5=36
  • O5=110
 LUT6
  • A1=19
  • A2=38
  • A3=62
  • A4=156
  • A5=87
  • A6=142
  • O6=179
 LUT_OR_MEM5
  • A1=5
  • A2=5
  • A3=6
  • A4=5
  • A5=6
  • CLK=5
  • DI1=5
  • O5=6
  • WE=5
 LUT_OR_MEM6
  • A1=46
  • A2=46
  • A3=46
  • A4=47
  • A5=47
  • A6=47
  • CLK=46
  • DI1=29
  • DI2=17
  • MC31=34
  • O6=47
  • WE=46
 PAD
  • PAD=13
 RAMB16BWER
  • ADDRA0=1
  • ADDRA1=1
  • ADDRA10=2
  • ADDRA11=2
  • ADDRA12=2
  • ADDRA13=2
  • ADDRA2=1
  • ADDRA3=1
  • ADDRA4=2
  • ADDRA5=2
  • ADDRA6=2
  • ADDRA7=2
  • ADDRA8=2
  • ADDRA9=2
  • ADDRB0=1
  • ADDRB1=1
  • ADDRB10=2
  • ADDRB11=2
  • ADDRB12=2
  • ADDRB13=2
  • ADDRB2=1
  • ADDRB3=1
  • ADDRB4=2
  • ADDRB5=2
  • ADDRB6=2
  • ADDRB7=2
  • ADDRB8=2
  • ADDRB9=2
  • CLKA=2
  • CLKB=2
  • DIA0=2
  • DIA1=2
  • DIA10=2
  • DIA11=2
  • DIA12=2
  • DIA13=2
  • DIA14=2
  • DIA15=2
  • DIA16=1
  • DIA17=1
  • DIA18=1
  • DIA19=1
  • DIA2=2
  • DIA20=1
  • DIA21=1
  • DIA22=1
  • DIA23=1
  • DIA24=1
  • DIA25=1
  • DIA26=1
  • DIA27=1
  • DIA28=1
  • DIA29=1
  • DIA3=2
  • DIA30=1
  • DIA31=1
  • DIA4=2
  • DIA5=2
  • DIA6=2
  • DIA7=2
  • DIA8=2
  • DIA9=2
  • DIB0=1
  • DIB1=1
  • DIB10=1
  • DIB11=1
  • DIB12=1
  • DIB13=1
  • DIB14=1
  • DIB15=1
  • DIB16=1
  • DIB17=1
  • DIB18=1
  • DIB19=1
  • DIB2=1
  • DIB20=1
  • DIB21=1
  • DIB22=1
  • DIB23=1
  • DIB24=1
  • DIB25=1
  • DIB26=1
  • DIB27=1
  • DIB28=1
  • DIB29=1
  • DIB3=1
  • DIB30=1
  • DIB31=1
  • DIB4=1
  • DIB5=1
  • DIB6=1
  • DIB7=1
  • DIB8=1
  • DIB9=1
  • DIPA0=2
  • DIPA1=2
  • DIPA2=1
  • DIPA3=1
  • DIPB0=1
  • DIPB1=1
  • DIPB2=1
  • DIPB3=1
  • DOA0=2
  • DOA1=2
  • DOA10=1
  • DOA2=2
  • DOA3=2
  • DOA4=2
  • DOA5=2
  • DOA6=2
  • DOA7=2
  • DOA8=1
  • DOA9=1
  • DOPA0=1
  • ENA=2
  • ENB=2
  • REGCEA=2
  • REGCEB=2
  • RSTA=2
  • RSTB=2
  • WEA0=2
  • WEA1=2
  • WEA2=2
  • WEA3=2
  • WEB0=2
  • WEB1=2
  • WEB2=2
  • WEB3=2
 RAMB16BWER_RAMB16BWER
  • ADDRA0=1
  • ADDRA1=1
  • ADDRA10=2
  • ADDRA11=2
  • ADDRA12=2
  • ADDRA13=2
  • ADDRA2=1
  • ADDRA3=1
  • ADDRA4=2
  • ADDRA5=2
  • ADDRA6=2
  • ADDRA7=2
  • ADDRA8=2
  • ADDRA9=2
  • ADDRB0=1
  • ADDRB1=1
  • ADDRB10=2
  • ADDRB11=2
  • ADDRB12=2
  • ADDRB13=2
  • ADDRB2=1
  • ADDRB3=1
  • ADDRB4=2
  • ADDRB5=2
  • ADDRB6=2
  • ADDRB7=2
  • ADDRB8=2
  • ADDRB9=2
  • CLKA=2
  • CLKB=2
  • DIA0=2
  • DIA1=2
  • DIA10=2
  • DIA11=2
  • DIA12=2
  • DIA13=2
  • DIA14=2
  • DIA15=2
  • DIA16=1
  • DIA17=1
  • DIA18=1
  • DIA19=1
  • DIA2=2
  • DIA20=1
  • DIA21=1
  • DIA22=1
  • DIA23=1
  • DIA24=1
  • DIA25=1
  • DIA26=1
  • DIA27=1
  • DIA28=1
  • DIA29=1
  • DIA3=2
  • DIA30=1
  • DIA31=1
  • DIA4=2
  • DIA5=2
  • DIA6=2
  • DIA7=2
  • DIA8=2
  • DIA9=2
  • DIB0=1
  • DIB1=1
  • DIB10=1
  • DIB11=1
  • DIB12=1
  • DIB13=1
  • DIB14=1
  • DIB15=1
  • DIB16=1
  • DIB17=1
  • DIB18=1
  • DIB19=1
  • DIB2=1
  • DIB20=1
  • DIB21=1
  • DIB22=1
  • DIB23=1
  • DIB24=1
  • DIB25=1
  • DIB26=1
  • DIB27=1
  • DIB28=1
  • DIB29=1
  • DIB3=1
  • DIB30=1
  • DIB31=1
  • DIB4=1
  • DIB5=1
  • DIB6=1
  • DIB7=1
  • DIB8=1
  • DIB9=1
  • DIPA0=2
  • DIPA1=2
  • DIPA2=1
  • DIPA3=1
  • DIPB0=1
  • DIPB1=1
  • DIPB2=1
  • DIPB3=1
  • DOA0=2
  • DOA1=2
  • DOA10=1
  • DOA2=2
  • DOA3=2
  • DOA4=2
  • DOA5=2
  • DOA6=2
  • DOA7=2
  • DOA8=1
  • DOA9=1
  • DOPA0=1
  • ENA=2
  • ENB=2
  • REGCEA=2
  • REGCEB=2
  • RSTA=2
  • RSTB=2
  • WEA0=2
  • WEA1=2
  • WEA2=2
  • WEA3=2
  • WEB0=2
  • WEB1=2
  • WEB2=2
  • WEB3=2
 RAMB8BWER
  • ADDRAWRADDR0=1
  • ADDRAWRADDR1=1
  • ADDRAWRADDR10=1
  • ADDRAWRADDR11=1
  • ADDRAWRADDR12=1
  • ADDRAWRADDR2=1
  • ADDRAWRADDR3=1
  • ADDRAWRADDR4=1
  • ADDRAWRADDR5=1
  • ADDRAWRADDR6=1
  • ADDRAWRADDR7=1
  • ADDRAWRADDR8=1
  • ADDRAWRADDR9=1
  • ADDRBRDADDR0=1
  • ADDRBRDADDR1=1
  • ADDRBRDADDR10=1
  • ADDRBRDADDR11=1
  • ADDRBRDADDR12=1
  • ADDRBRDADDR2=1
  • ADDRBRDADDR3=1
  • ADDRBRDADDR4=1
  • ADDRBRDADDR5=1
  • ADDRBRDADDR6=1
  • ADDRBRDADDR7=1
  • ADDRBRDADDR8=1
  • ADDRBRDADDR9=1
  • CLKAWRCLK=1
  • CLKBRDCLK=1
  • DIADI0=1
  • DIADI1=1
  • DIADI10=1
  • DIADI11=1
  • DIADI12=1
  • DIADI13=1
  • DIADI14=1
  • DIADI15=1
  • DIADI2=1
  • DIADI3=1
  • DIADI4=1
  • DIADI5=1
  • DIADI6=1
  • DIADI7=1
  • DIADI8=1
  • DIADI9=1
  • DIBDI0=1
  • DIBDI1=1
  • DIBDI10=1
  • DIBDI11=1
  • DIBDI12=1
  • DIBDI13=1
  • DIBDI14=1
  • DIBDI15=1
  • DIBDI2=1
  • DIBDI3=1
  • DIBDI4=1
  • DIBDI5=1
  • DIBDI6=1
  • DIBDI7=1
  • DIBDI8=1
  • DIBDI9=1
  • DIPADIP0=1
  • DIPADIP1=1
  • DIPBDIP0=1
  • DIPBDIP1=1
  • DOADO0=1
  • DOADO1=1
  • DOADO2=1
  • DOADO3=1
  • ENAWREN=1
  • ENBRDEN=1
  • REGCEA=1
  • REGCEBREGCE=1
  • RSTA=1
  • RSTBRST=1
  • WEAWEL0=1
  • WEAWEL1=1
  • WEBWEU0=1
  • WEBWEU1=1
 RAMB8BWER_RAMB8BWER
  • ADDRAWRADDR0=1
  • ADDRAWRADDR1=1
  • ADDRAWRADDR10=1
  • ADDRAWRADDR11=1
  • ADDRAWRADDR12=1
  • ADDRAWRADDR2=1
  • ADDRAWRADDR3=1
  • ADDRAWRADDR4=1
  • ADDRAWRADDR5=1
  • ADDRAWRADDR6=1
  • ADDRAWRADDR7=1
  • ADDRAWRADDR8=1
  • ADDRAWRADDR9=1
  • ADDRBRDADDR0=1
  • ADDRBRDADDR1=1
  • ADDRBRDADDR10=1
  • ADDRBRDADDR11=1
  • ADDRBRDADDR12=1
  • ADDRBRDADDR2=1
  • ADDRBRDADDR3=1
  • ADDRBRDADDR4=1
  • ADDRBRDADDR5=1
  • ADDRBRDADDR6=1
  • ADDRBRDADDR7=1
  • ADDRBRDADDR8=1
  • ADDRBRDADDR9=1
  • CLKAWRCLK=1
  • CLKBRDCLK=1
  • DIADI0=1
  • DIADI1=1
  • DIADI10=1
  • DIADI11=1
  • DIADI12=1
  • DIADI13=1
  • DIADI14=1
  • DIADI15=1
  • DIADI2=1
  • DIADI3=1
  • DIADI4=1
  • DIADI5=1
  • DIADI6=1
  • DIADI7=1
  • DIADI8=1
  • DIADI9=1
  • DIBDI0=1
  • DIBDI1=1
  • DIBDI10=1
  • DIBDI11=1
  • DIBDI12=1
  • DIBDI13=1
  • DIBDI14=1
  • DIBDI15=1
  • DIBDI2=1
  • DIBDI3=1
  • DIBDI4=1
  • DIBDI5=1
  • DIBDI6=1
  • DIBDI7=1
  • DIBDI8=1
  • DIBDI9=1
  • DIPADIP0=1
  • DIPADIP1=1
  • DIPBDIP0=1
  • DIPBDIP1=1
  • DOADO0=1
  • DOADO1=1
  • DOADO2=1
  • DOADO3=1
  • ENAWREN=1
  • ENBRDEN=1
  • REGCEA=1
  • REGCEBREGCE=1
  • RSTA=1
  • RSTBRST=1
  • WEAWEL0=1
  • WEAWEL1=1
  • WEBWEU0=1
  • WEBWEU1=1
 REG_SR
  • CE=82
  • CK=255
  • D=255
  • Q=255
  • SR=150
 SELMUX2_1
  • 0=11
  • 1=11
  • OUT=11
  • S0=11
 SLICEL
  • A4=25
  • A5=3
  • A6=18
  • AMUX=1
  • AQ=29
  • AX=8
  • B=1
  • B4=26
  • B5=4
  • B6=17
  • BQ=26
  • BX=6
  • C1=2
  • C2=2
  • C3=2
  • C4=24
  • C5=5
  • C6=15
  • CE=13
  • CIN=21
  • CLK=30
  • CMUX=2
  • COUT=17
  • CQ=22
  • CX=8
  • D1=1
  • D2=2
  • D3=2
  • D4=21
  • D5=5
  • D6=14
  • DMUX=1
  • DQ=19
  • DX=6
  • SR=20
 SLICEM
  • A=4
  • A1=14
  • A2=14
  • A3=15
  • A4=15
  • A5=15
  • A6=15
  • AI=5
  • AMUX=5
  • AQ=3
  • AX=10
  • B=1
  • B1=12
  • B2=12
  • B3=12
  • B4=12
  • B5=12
  • B6=12
  • BI=3
  • BMUX=3
  • BQ=3
  • BX=8
  • C=2
  • C1=11
  • C2=11
  • C3=11
  • C4=11
  • C5=11
  • C6=11
  • CE=15
  • CI=3
  • CLK=15
  • CMUX=2
  • COUT=4
  • CQ=3
  • CX=10
  • D1=9
  • D2=9
  • D3=9
  • D4=9
  • D5=9
  • D6=9
  • DI=6
  • DMUX=11
  • DQ=2
  • DX=8
 SLICEX
  • A=17
  • A1=7
  • A2=14
  • A3=20
  • A4=23
  • A5=27
  • A6=24
  • AMUX=14
  • AQ=55
  • AX=47
  • B=15
  • B1=7
  • B2=11
  • B3=20
  • B4=21
  • B5=27
  • B6=21
  • BMUX=13
  • BQ=37
  • BX=30
  • C=12
  • C1=3
  • C2=7
  • C3=14
  • C4=15
  • C5=22
  • C6=17
  • CE=17
  • CLK=73
  • CMUX=11
  • CQ=29
  • CX=22
  • D=13
  • D1=1
  • D2=7
  • D3=12
  • D4=13
  • D5=21
  • D6=16
  • DMUX=13
  • DQ=27
  • DX=24
  • SR=49
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_compxlibgui 1 1 0 0 0 0 0
_impact 7 6 0 0 0 0 0
bitgen 17 17 0 0 0 0 0
bitinit 1 1 0 0 0 0 0
cse_server 1 1 0 0 0 0 0
edif2ngd 7 7 0 0 0 0 0
elfcheck 117 117 0 0 0 0 0
libgen 14 14 0 0 0 0 0
map 21 19 0 0 0 0 0
netgen 7 7 0 0 0 0 0
ngc2edif 8 8 0 0 0 0 0
ngcbuild 56 56 0 0 0 0 0
ngdbuild 21 21 0 0 0 0 0
obngc 5 5 0 0 0 0 0
par 19 19 0 0 0 0 0
partgen 58 54 0 0 0 0 0
platgen 11 11 0 0 0 0 0
psf2Edward 10 10 0 0 0 0 0
trce 18 18 0 0 0 0 0
xps 23 20 0 0 0 0 0
xpwr 2 2 0 0 0 0 0
xst 152 152 0 0 0 0 0
 
Core Statistics
Core Type=dds_compiler_v4_0
c_accumulator_width=26 c_amplitude=0 c_channels=1 c_has_ce=1
c_has_channel_index=0 c_has_phase_out=0 c_has_phasegen=1 c_has_rdy=0
c_has_rfd=0 c_has_sclr=0 c_has_sincos=1 c_latency=-1
c_mem_type=1 c_negative_cosine=0 c_negative_sine=0 c_noise_shaping=0
c_optimise_goal=0 c_output_width=12 c_outputs_required=0 c_phase_angle_width=12
c_phase_increment=2 c_phase_increment_value=101000111101011100001 c_phase_offset=0 c_phase_offset_value=0
c_por_mode=0 c_use_dsp48=0 c_xdevicefamily=spartan6
Core Type=sysgen_core
clock_period=20.00000000 clocking=Clock_Enables compilation=Bitstream sample_periods=1.00000000000
testbench=0 total_blocks=9 xilinx_chipscope_block=1 xilinx_dds_compiler_4_0_block=1
xilinx_gateway_out_block=1 xilinx_system_generator_block=1
Core Type=chipscope_icon_v1_05_a
c_build_revision=0 c_core_major_ver=1 c_core_minor_alpha_ver=97 c_core_minor_ver=5
c_core_type=1 c_example_design=false c_major_version=13 c_mfg_id=1
c_minor_version=2 c_num_control_ports=1 c_part_idcode_register=0 c_use_bufr=0
c_use_control0=1 c_use_control1=0 c_use_control10=0 c_use_control11=0
c_use_control12=0 c_use_control13=0 c_use_control14=0 c_use_control2=0
c_use_control3=0 c_use_control4=0 c_use_control5=0 c_use_control6=0
c_use_control7=0 c_use_control8=0 c_use_control9=0 c_use_ext_bscan=0
c_use_jtag_bufg=1 c_use_new_parser=0 c_use_sim=0 c_use_softbscan=0
c_use_unused_bscan=0 c_use_xst_tck_workaround=1 c_user_scan_chain=1 c_xco_list=Number_Control_Ports=1;Use_Ext_Bscan=false;User_Scan_Chain=USER1;Enable_Jtag_Bufg=true;Use_Unused_Bscan=false;Use_Softbscan=false
c_xdevicefamily=spartan6
Core Type=chipscope_ila_v1_04_a
c_build_revision=0 c_core_major_ver=1 c_core_minor_alpha_ver=97 c_core_minor_ver=4
c_core_type=2 c_data_depth=2048 c_data_width=1 c_example_design=false
c_ext_cap_pin_mode=0 c_ext_cap_rate_mode=0 c_ext_cap_use_reg=1 c_m0_tpid=0
c_m0_type=0 c_m10_tpid=10 c_m10_type=0 c_m11_tpid=11
c_m11_type=0 c_m12_tpid=12 c_m12_type=0 c_m13_tpid=13
c_m13_type=0 c_m14_tpid=14 c_m14_type=0 c_m15_tpid=15
c_m15_type=0 c_m1_tpid=1 c_m1_type=0 c_m2_tpid=2
c_m2_type=0 c_m3_tpid=3 c_m3_type=0 c_m4_tpid=4
c_m4_type=0 c_m5_tpid=5 c_m5_type=0 c_m6_tpid=6
c_m6_type=0 c_m7_tpid=7 c_m7_type=0 c_m8_tpid=8
c_m8_type=0 c_m9_tpid=9 c_m9_type=0 c_major_version=13
c_mcnt0_width=1 c_mcnt10_width=1 c_mcnt11_width=1 c_mcnt12_width=1
c_mcnt13_width=1 c_mcnt14_width=1 c_mcnt15_width=1 c_mcnt1_width=1
c_mcnt2_width=1 c_mcnt3_width=1 c_mcnt4_width=1 c_mcnt5_width=1
c_mcnt6_width=1 c_mcnt7_width=1 c_mcnt8_width=1 c_mcnt9_width=1
c_mfg_id=1 c_minor_version=2 c_num_ext_cap_pins=8 c_num_match_units=1
c_num_tseq_cnt=0 c_num_tseq_states=1 c_ram_type=1 c_srl16_type=2
c_tc_mcnt_width=1 c_timestamp_depth=512 c_timestamp_type=0 c_timestamp_width=32
c_trig0_width=12 c_trig10_width=1 c_trig11_width=1 c_trig12_width=1
c_trig13_width=1 c_trig14_width=1 c_trig15_width=1 c_trig1_width=1
c_trig2_width=1 c_trig3_width=1 c_trig4_width=1 c_trig5_width=1
c_trig6_width=1 c_trig7_width=1 c_trig8_width=1 c_trig9_width=1
c_tseq_cnt0_width=1 c_tseq_cnt1_width=1 c_tseq_type=0 c_use_atc_clkin=0
c_use_data=0 c_use_gap=0 c_use_inv_clk=0 c_use_mcnt0=0
c_use_mcnt1=0 c_use_mcnt10=0 c_use_mcnt11=0 c_use_mcnt12=0
c_use_mcnt13=0 c_use_mcnt14=0 c_use_mcnt15=0 c_use_mcnt2=0
c_use_mcnt3=0 c_use_mcnt4=0 c_use_mcnt5=0 c_use_mcnt6=0
c_use_mcnt7=0 c_use_mcnt8=0 c_use_mcnt9=0 c_use_rpm=0
c_use_storage_qual=1 c_use_tc_mcnt=0 c_use_trig0=1 c_use_trig1=0
c_use_trig10=0 c_use_trig11=0 c_use_trig12=0 c_use_trig13=0
c_use_trig14=0 c_use_trig15=0 c_use_trig2=0 c_use_trig3=0
c_use_trig4=0 c_use_trig5=0 c_use_trig6=0 c_use_trig7=0
c_use_trig8=0 c_use_trig9=0 c_use_trig_out=0 c_use_trigdata0=1
c_use_trigdata1=0 c_use_trigdata10=0 c_use_trigdata11=0 c_use_trigdata12=0
c_use_trigdata13=0 c_use_trigdata14=0 c_use_trigdata15=0 c_use_trigdata2=0
c_use_trigdata3=0 c_use_trigdata4=0 c_use_trigdata5=0 c_use_trigdata6=0
c_use_trigdata7=0 c_use_trigdata8=0 c_use_trigdata9=0 c_xco_list=Component_Name=ila_1_04_a_931ec98e70229a14;Number_Of_Trigger_Ports=1;Max_Sequence_Levels=1;Use_RPMs=false;Enable_Trigger_Output_Port=false;Sample_On=Rising;Sample_Data_Depth=2048;Enable_Storage_Qualification=true;Data_Same_As_Trigger=true;Data_Port_Width=0;Trigger_Port_Width_1=12;Match_Units_1=1;Counter_Width_1=Disabled;Match_Type_1=basic;Exclude_From_Data_Storage_1=false;Trigger_Port_Width_2=8;Match_Units_2=1;Counter_Width_2=Disabled;Match_Type_2=basic_with_edges;Exclude_From_Data_Storage_2=false;Trigger_Port_Width_3=8;Match_Units_3=1;Counter_Width_3=Disabled;Match_Type_3=basic_with_edges;Exclude_From_Data_Storage_3=false;Trigger_Port_Width_4=8;Match_Units_4=1;Counter_Width_4=Disabled;Match_Type_4=basic_with_edges;Exclude_From_Data_Storage_4=false;Trigger_Port_Width_5=8;Match_Units_5=1;Counter_Width_5=Disabled;Match_Type_5=basic_with_edges;Exclude_From_Data_Storage_5=false;Trigger_Port_Width_6=8;Match_Units_6=1;Counter_Width_6=Disabled;Match_Type_6=basic_with_edges;Exclude_From_Data_Storage_6=false;Trigger_Port_Width_7=8;Match_Units_7=1;Counter_Width_7=Disabled;Match_Type_7=basic_with_edges;Exclude_From_Data_Storage_7=false;Trigger_Port_Width_8=8;Match_Units_8=1;Counter_Width_8=Disabled;Match_Type_8=basic_with_edges;Exclude_From_Data_Storage_8=false;Trigger_Port_Width_9=8;Match_Units_9=1;Counter_Width_9=Disabled;Match_Type_9=basic_with_edges;Exclude_From_Data_Storage_9=false;Trigger_Port_Width_10=8;Match_Units_10=1;Counter_Width_10=Disabled;Match_Type_10=basic_with_edges;Exclude_From_Data_Storage_10=false;Trigger_Port_Width_11=8;Match_Units_11=1;Counter_Width_11=Disabled;Match_Type_11=basic_with_edges;Exclude_From_Data_Storage_11=false;Trigger_Port_Width_12=8;Match_Units_12=1;Counter_Width_12=Disabled;Match_Type_12=basic_with_edges;Exclude_From_Data_Storage_12=false;Trigger_Port_Width_13=8;Match_Units_13=1;Counter_Width_13=Disabled;Match_Type_13=basic_with_edges;Exclude_From_Data_Storage_13=false;Trigger_Port_Width_14=8;Match_Units_14=1;Counter_Width_14=Disabled;Match_Type_14=basic_with_edges;Exclude_From_Data_Storage_14=false;Trigger_Port_Width_15=8;Match_Units_15=1;Counter_Width_15=Disabled;Match_Type_15=basic_with_edges;Exclude_From_Data_Storage_15=false;Trigger_Port_Width_16=8;Match_Units_16=1;Counter_Width_16=Disabled;Match_Type_16=basic_with_edges;Exclude_From_Data_Storage_16=false
c_xdevicefamily=spartan6
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BSCAN_SPARTAN6=1 NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=26
NGDBUILD_NUM_FDC=9 NGDBUILD_NUM_FDCE=16 NGDBUILD_NUM_FDE=133 NGDBUILD_NUM_FDP=14
NGDBUILD_NUM_FDR=50 NGDBUILD_NUM_FDRE=75 NGDBUILD_NUM_FDS=10 NGDBUILD_NUM_GND=5
NGDBUILD_NUM_INV=6 NGDBUILD_NUM_LDC=1 NGDBUILD_NUM_LUT1=57 NGDBUILD_NUM_LUT2=69
NGDBUILD_NUM_LUT3=31 NGDBUILD_NUM_LUT4=87 NGDBUILD_NUM_LUT5=2 NGDBUILD_NUM_LUT6=24
NGDBUILD_NUM_MUXCY=48 NGDBUILD_NUM_MUXCY_L=67 NGDBUILD_NUM_MUXF7=9 NGDBUILD_NUM_MUXF8=2
NGDBUILD_NUM_OBUF=12 NGDBUILD_NUM_RAMB16BWER=2 NGDBUILD_NUM_RAMB8BWER=1 NGDBUILD_NUM_SRL16=12
NGDBUILD_NUM_SRL16E=1 NGDBUILD_NUM_SRLC16E=10 NGDBUILD_NUM_SRLC32E=29 NGDBUILD_NUM_VCC=4
NGDBUILD_NUM_XORCY=103
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BSCAN_SPARTAN6=1 NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_FD=26 NGDBUILD_NUM_FDC=9
NGDBUILD_NUM_FDCE=16 NGDBUILD_NUM_FDE=133 NGDBUILD_NUM_FDP=14 NGDBUILD_NUM_FDR=50
NGDBUILD_NUM_FDRE=75 NGDBUILD_NUM_FDS=10 NGDBUILD_NUM_GND=6 NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_INV=6 NGDBUILD_NUM_LDC=1 NGDBUILD_NUM_LUT1=57 NGDBUILD_NUM_LUT2=69
NGDBUILD_NUM_LUT3=31 NGDBUILD_NUM_LUT4=87 NGDBUILD_NUM_LUT5=2 NGDBUILD_NUM_LUT6=24
NGDBUILD_NUM_MUXCY=48 NGDBUILD_NUM_MUXCY_L=67 NGDBUILD_NUM_MUXF7=9 NGDBUILD_NUM_MUXF8=2
NGDBUILD_NUM_OBUF=12 NGDBUILD_NUM_RAMB16BWER=2 NGDBUILD_NUM_RAMB8BWER=1 NGDBUILD_NUM_SRL16E=13
NGDBUILD_NUM_SRLC16E=10 NGDBUILD_NUM_SRLC32E=29 NGDBUILD_NUM_TIMESPEC=1 NGDBUILD_NUM_TS_TIMESPEC=1
NGDBUILD_NUM_VCC=5 NGDBUILD_NUM_XORCY=103